1. Field of the Invention
The present invention relates to a method for producing a semiconductor device and a semiconductor device and, in particular, to a method for producing a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a pillar-shaped structure, and the semiconductor device.
2. Description of the Related Art
Solid-state imaging devices such as CCDs and CMOS devices are widely used for video cameras, still cameras, and the like. Improvements in the performances of solid-state imaging devices such as a higher resolution, a higher operation speed, and a higher sensitivity have been demanded.
As illustrated in FIG. 17, a solid-state imaging device in which a single pixel is constituted within a single pillar-shaped semiconductor 110 is known (for example, refer to International Publication No. 2009/034623).
In this pixel structure, an N+-type silicon layer 51 functioning as a signal line of the solid-state imaging device is formed on a semiconductor substrate. The pillar-shaped semiconductor 110 is connected to the N+-type silicon layer 51. In the pillar-shaped semiconductor 110, a MOS transistor is formed that is constituted by a P-type silicon layer 52, insulating films 53a and 53b, and gate conductor layers 54a and 54b and is configured to discharge stored charges. In addition, in the pillar-shaped semiconductor 110, a photodiode that is connected to the MOS transistor and is configured to store charges generated through irradiation with light (electromagnetic energy waves) is formed. This photodiode is constituted by the P-type silicon layer 52 and N-type silicon layers 58a and 58b. A junction field-effect transistor (junction transistor) is formed in which the P-type semiconductor 52 surrounded by the photodiode serves as a channel, the photodiode serves as a gate, a P+-type silicon layer 56 that is formed on the photodiode and is connected to pixel selection wirings 57a and 57b serves as a source, and a portion of the P-type silicon layer 52 close to the N+-type silicon layer 51 serves as a drain.
The basic operations of the solid-state imaging device are a signal-charge storage operation of storing, in the photodiode, signal charges (in this case, electrons) generated by irradiation with light; a signal reading operation of modulating a source-drain current flowing between the portion of the P-type silicon layer 52 close to the N+-type silicon layer 51 and the P+-type silicon layer 56, with a gate voltage based on a photodiode voltage according to the stored signal charges, and reading the modulated source-drain current as a signal current; and a reset operation of, after the signal reading operation is completed, discharging the signal charges stored in the photodiode to the N+-type silicon layer 51 by the application of on-voltage to the gate conductor layers 54a and 54b of the MOS transistor.
In a two-dimensional solid-state imaging device, such pixels illustrated in FIG. 17 are two-dimensionally arranged in a light-sensitive region. The signal reading operation is performed by transmitting pixel signals (signal current) via the N+-type silicon layer 51 to an output circuit disposed around the light-sensitive region. The reset operation is also performed by electric transmission between pixels and the circuit around the light-sensitive region. To increase the number of pixels or the number of images read per unit time in a solid-state imaging device, the speed of performing the signal reading operation needs to be increased. Accordingly, a decrease in the electrical resistance of the N+-type silicon layer 51 functioning as a signal line is required.
To achieve the decrease in the electrical resistance of the N+-type silicon layer 51, as illustrated in FIG. 18A, a structure may be conceived in which a metal layer 59 formed on a silicon substrate 60 is joined to the back surface of the N+-type silicon layer 51. In this structure, the electrical resistance of the signal line is substantially determined by the metal layer 59 and hence the above-described increase in the speed of performing the signal reading operation is achieved. However, it is difficult to form the metal layer 59 joined to the N+-type silicon layer 51 in view of the joining affinity between metal material and silicon material.
The metal layer 59 may be formed on the silicon substrate 60 by the following method. As illustrated in FIG. 18B, a silicon oxide layer 62 is formed on a semiconductor substrate 61. The metal layer 59 is formed on the silicon oxide layer 62. The semiconductor substrate 61 on which the metal layer 59 has been formed is bonded to a semiconductor substrate 64. After that, pixels are formed in portions indicated by dotted lines in the semiconductor substrate 64 in FIG. 18B. The single dot-dashed line D-D′ in FIG. 18B indicates a state where the semiconductor substrate 64 is shaped so as to have a predetermined height by subjecting the semiconductor substrate 64 to polishing, etching, or another separation method.
However, since the metal layer 59 and the semiconductor substrate 64 are directly bonded together by this production method, the semiconductor substrates 61 and 64 become warped, cracked, or separated due to the difference in thermal expansion coefficient between the metal layer 59 and the semiconductor substrate 64. It is technically important to develop the method of directly bonding the metal layer 59 to the back surface of the N+-type silicon layer 51 without warping, cracking, or separation as illustrated in FIG. 18A for the purpose of increasing the speed of performing the signal reading operation.
The achievements of a higher degree of integration and higher performances of semiconductor devices other than solid-state imaging devices and circuit elements incorporated in semiconductor devices by overcoming of the problems have been strongly demanded.
To achieve an increase in the speed of performing the signal reading operation, there is an SGT (surrounding gate transistor) (hereafter, simply abbreviated as “SGT”) that is a vertical MOS transistor having a structure in which a side surface of a pillar-shaped semiconductor having a pillar-shaped structure is used as a channel region and a gate electrode surrounds the channel region (for example, refer to U.S. Patent Application Publication No. 2010/0213539 (A1)).
In such an SGT, as illustrated in FIG. 19, a planar silicon film 67 is formed on a buried-oxide substrate 66; and the planar silicon film 67 and a pillar-shaped silicon layer 68 form a pillar-shaped structure. In the planar silicon film 67, a P+-type silicon diffusion layer 69 functioning as a drain is formed. A P+-type silicon diffusion layer 70 functioning as a source is formed in an upper portion of the pillar-shaped silicon layer 68. A gate insulating layer 71 is formed on an outer peripheral portion of the pillar-shaped silicon layer 68. A gate electrode 72 is formed on an outer peripheral portion of the gate insulating layer 71. Thus, a P-type channel SGT in which the pillar-shaped silicon layer 68 between the P+-type silicon diffusion layer 69 and the P+-type silicon diffusion layer 70 serves as a channel is formed.
A silicon nitride (SiN) film 73 and a silicon oxide (SiO2) film 74 are formed so as to surround the gate electrode 72, the P+-type silicon diffusion layer 70, and the P+-type silicon diffusion layer 69. A contact hole 75 is formed in the silicon oxide layer 74. The P+-type silicon diffusion layer 70 is connected to source metal wiring 76 via the contact hole 75. Thus, a P-channel SGT is formed.
The P+-type silicon diffusion layer 69 illustrated in FIG. 19 is connected to metal wiring (not shown) in a predetermined portion that is a coplanar extension of the planar silicon film 67. To further increase the speed of performing the signal reading operation in a semiconductor device including an SGT, the connection between the P+-type silicon diffusion layer 69 and the metal wiring needs to be achieved in a short distance as in the P+-type silicon diffusion layer 70.
However, in the SGT illustrated in FIG. 19, an electrical resistance corresponding to the distance between the metal wiring and the P+-type silicon diffusion layer 69 or the distance to the drain end of the channel of the SGT in the P+-type silicon diffusion layer 69 is present. Accordingly, as in a solid-state imaging device, to increase the speed of performing the signal reading operation in a semiconductor device including an SGT, it is necessary to directly bond a metal layer to the back surface of the P+-type silicon diffusion layer 69 to thereby decrease the electrical resistance.
As described above, the signal reading operation in a two-dimensional solid-state imaging device is performed by transmitting pixel signals (signal current) to an external circuit disposed around the light-sensitive region via the N+-type silicon layer 51 functioning as a signal line. The reset operation is also performed by electric transmission between pixels and the external circuit outside the light-sensitive region. The responsivity of the electric transmission is considerably influenced by the electrical resistance and parasitic capacitance of the wiring connecting the pixels and the peripheral circuit. To increase the number of pixels or the number of images read per unit time in a solid-state imaging device, the electrical resistance of the wiring needs to be decreased.
In a solid-state imaging device illustrated in FIG. 17, the electrical resistance is substantially determined by the electrical resistance of the N+-type silicon layer 51. The N+-type silicon layer 51 is formed by doping a silicon (Si) semiconductor with a donor impurity such as phosphorus (P) or arsenic (As) by ion doping (ion implantation). Accordingly, the electrical resistance of the N+-type silicon layer 51 cannot be made smaller than the electrical resistance of metals that are used in standard semiconductor devices such as aluminum (Al), copper (Cu), tungsten (W), and nickel (Ni). Thus, the solid-state imaging device illustrated in FIG. 17 has a problem that it is inferior in a high-speed operation property to a solid-state imaging device in which the electrical connection between pixels and the peripheral circuit is established via metal wiring.
In a pixel structure in which an N+-type silicon layer is horizontally expanded in pixels and the electrical connection between the pixels and the peripheral circuit is established via metal wiring connected through contact holes formed in the extension regions, the degree of integration of the pixels is decreased.
As described above, in the SGT illustrated in FIG. 19, the P+-type silicon diffusion layer 69 is also connected to metal wiring in an extension portion of the planar silicon film 67. In this manner of connecting the P+-type silicon diffusion layer 69 and the metal wiring, a short-distance connection as in the connection between the P+-type silicon diffusion layer 70 and the metal wiring cannot be formed. Accordingly, an electrical resistance between the metal wiring and an end of the P+-type silicon diffusion layer 69 closest to the channel of the SGT is present. Accordingly, to further increase the operation speed in a semiconductor device including an SGT, the electrical resistance needs to be decreased.